NASA’s Next-Gen Space Processor for More Autonomous Spacecraft

Key Takeaways

• NASA’s HPSC processor testing marks a major step toward faster onboard spacecraft computing.
• The processor targets autonomy, science data handling, landing support, and crewed exploration.
• Microchip’s PIC64-HPSC family links NASA mission needs with commercial aerospace demand.

NASA Next-Gen Space Processor Testing Moves Flight Computing Toward Autonomy

The National Aeronautics and Space Administration (NASA) announced on May 12, 2026, that its NASA next-gen space processor has entered a testing phase at the agency’s Jet Propulsion Laboratory (JPL) in Southern California. The processor belongs to NASA’s High Performance Spaceflight Computing project, usually shortened to HPSC, and NASA describes it as a radiation-hardened, high-performance system intended to deliver a large increase in spacecraft computing capacity.

The testing milestone matters because spacecraft computing has long faced a trade between reliability and speed. Space processors must tolerate radiation, temperature swings, launch vibration, and mission lifetimes measured in years. That environment has kept many missions dependent on older but trusted processor designs, even as instruments, sensors, cameras, navigation software, and autonomy systems have grown more demanding.

HPSC does not replace every spacecraft computer problem with one chip. It gives future mission designers a stronger onboard computing option for tasks that cannot wait for ground control. That includes real-time landing decisions, onboard science data review, image processing, instrument coordination, crewed habitat support, and autonomous responses during deep-space operations.

NASA says JPL testing began in February 2026 and will continue for several months. Early indications reported by NASA show the processor working as designed and operating at 500 times the performance of the radiation-hardened chips in use today. NASA also describes the project target as up to 100 times the computational capacity of existing spaceflight computers, a broader program benchmark tied to mission-class capability rather than a single test comparison.

The processor’s name may sound like an incremental hardware update, but the program reflects a broader shift in spacecraft design. Modern missions increasingly need onboard machines that can sort, reduce, interpret, and act on data before sending the most valuable results back to Earth. That shift affects planetary science, Earth observation, lunar surface systems, commercial satellite platforms, defense and security users, and human exploration missions that cannot rely on instant help from Earth.

Why Spacecraft Processors Lag Behind Terrestrial Chips

Consumer electronics and cloud computing hardware can accept a faster replacement cycle. Spacecraft cannot. A phone or server processor can be replaced, patched, cooled, or redesigned after field problems emerge. A spacecraft processor may need to keep working after launch vibration, radiation exposure, thermal cycling, vacuum, dust, and years of limited physical access.

Radiation is one reason spacecraft computers often look old compared with terrestrial systems. High-energy particles from the Sun and beyond the solar system can flip bits, damage circuits, corrupt memory, or cause system faults. Designers protect against those effects through radiation hardening, error correction, redundancy, shielding, careful manufacturing, and conservative qualification.

The result is a cautious culture in flight computing. Missions value parts that have known behavior, documented failure modes, and flight heritage. A processor that seems slow by desktop standards can still be preferable if engineers trust it on a multibillion-dollar mission. The cost of an unplanned safe-mode event, a failed landing decision, or a lost science campaign can exceed the benefit of using an unproven faster part.

Older spacecraft processors also reflect the long development cycle of major missions. A planetary spacecraft may lock its avionics design years before launch. Once engineers build the software, validate interfaces, and qualify the flight computer, a late processor swap can trigger schedule, cost, and risk problems. That explains why spacecraft can fly with computing technology that began development many years before the mission reaches its destination.

HPSC addresses that bottleneck by combining radiation tolerance, stronger performance, power control, networking, and modern software support in one space-qualified processor family. NASA’s HPSC page describes a need for autonomy, artificial intelligence (AI), machine learning (ML), image and signal processing, data flow management, and object detection. Those tasks require more processing capacity than legacy systems can comfortably provide on many advanced missions.

What HPSC Adds to Spacecraft Computing

NASA describes HPSC as a system-on-a-chip, or SoC, meaning the device combines many computer functions on one integrated chip rather than spreading them across separate boards. The processor includes central processing units, computational support blocks, networking units, memory interfaces, and input/output interfaces. That compact design can reduce mass, volume, and power demand compared with larger distributed computing assemblies.

Microchip markets the processor family as PIC64-HPSC, a set of 64-bit microprocessor units built for space applications. The family includes the PIC64-HPSC1000 radiation-hardened microprocessor unit for medium Earth orbit, geostationary Earth orbit, and deep-space mission profiles, and the PIC64-HPSC1100 radiation-tolerant microprocessor unit for low Earth orbit and commercial satellite applications.

The architecture uses RISC-V, an open instruction set architecture that has attracted interest in embedded systems, research hardware, and specialized processors. Microchip says the PIC64-HPSC family includes multiple 64-bit RISC-V cores, vector processing, AI and ML processing support, secure boot, crypto acceleration, Time-Sensitive Networking (TSN), SpaceWire, Peripheral Component Interconnect Express (PCIe), and Compute Express Link (CXL) 2.0.

That combination gives HPSC a different profile from a legacy single-purpose flight processor. It can support mission software that divides work among processor cores, accelerates certain data-heavy operations, and connects directly to sensors, instruments, and other onboard systems. It also allows unused functions to shift into lower-power states, which matters for spacecraft that manage tight energy budgets.

The project’s fault-tolerant design is as important as its speed. Spacecraft autonomy only helps if the computer can produce reliable results under harsh conditions. HPSC must demonstrate that its performance survives radiation, thermal stress, mechanical shock, and realistic mission workloads before NASA can treat it as ready for flight use.

The following table summarizes several HPSC attributes that matter for mission design.

JPL Testing Tests the Chip Against Space-Like Stress

JPL’s test campaign exposes the HPSC chips to radiation, thermal, shock, performance, and functional testing. Those categories reflect the practical barriers between an impressive laboratory processor and a flight-qualified processor. A chip must handle expected workloads, survive environmental stress, and behave predictably when faults occur.

Radiation testing examines how the device responds to energetic particles that can disrupt electronics. Thermal testing checks operation under temperature conditions relevant to spacecraft environments. Shock testing relates to mechanical stresses that can occur during launch, deployment, landing, or other mission events. Functional testing checks whether the processor carries out expected operations under controlled scenarios.

NASA’s announcement also says the team is testing the processor with high-fidelity landing scenarios from real NASA missions. Those scenarios matter because planetary landing can produce intense computing demand over a short period. Sensors may gather high-volume terrain, velocity, and hazard data at the same time that guidance software must make fast decisions. A spacecraft cannot pause descent and wait for a ground team to calculate the next move.

The testing campaign also reflects NASA’s need to compare raw speed with dependable performance. A processor that runs fast in benign conditions may fail qualification if radiation exposure produces too many errors, if thermal limits reduce operation, or if mission software cannot use the hardware effectively. Spaceflight computing is a systems problem involving silicon, board design, operating systems, compilers, interfaces, power electronics, memory, sensors, and fault management.

NASA’s reported “Hello Universe” email at the start of testing served as a symbolic milestone rather than a qualification result. The more meaningful evidence will come from the months-long test program and subsequent mission adoption decisions. As of May 2026, HPSC is under test, not yet a routine flight processor across NASA missions.

Autonomy Needs Drive Demand for More Onboard Computing

Deep-space missions often operate with communication delays that prevent real-time control from Earth. A command sent to Mars can take minutes to arrive, and a response can take minutes to return. Outer solar system missions face longer delays. During landing, flyby observations, safe-mode recovery, or fast-changing science events, a spacecraft may need to evaluate conditions without waiting for human direction.

HPSC addresses that problem by giving spacecraft more computing capacity near the sensors and instruments that generate data. A rover could process images before deciding where to drive. An orbiter could prioritize science observations before a downlink window. A lander could interpret hazard data during descent. A habitat computer could monitor systems and filter alerts for crew and ground teams.

This does not mean spacecraft will become independent in a human sense. Mission rules, flight software, safety limits, and ground planning will still govern operations. The processor simply gives software more room to make bounded decisions, filter data, and respond within mission-approved constraints.

NASA’s Safe and Precise Landing Integrated Capabilities Evolution work illustrates the kind of computing burden involved in landing. Precision landing relies on avionics, sensors, algorithms, navigation, and hazard assessment. Better flight processors can help integrate these functions in real time, particularly for landings near scientifically valuable terrain that may contain rocks, slopes, shadows, or other hazards.

Science missions face a related problem. Instruments can collect more data than a spacecraft can store or transmit. More onboard computing lets missions compress, classify, or prioritize data before downlink. That can increase the value of limited communications sessions without requiring every raw observation to travel back to Earth first.

NASA and Microchip Built HPSC as a Commercial Partnership

NASA selected Microchip Technology of Chandler, Arizona, in August 2022 to develop the HPSC processor. Under the contract, Microchip would architect, design, and deliver the processor over three years, with a goal of use in future lunar and planetary missions. NASA’s 2022 contract announcement described a processor that would provide at least 100 times the computational capacity of existing spaceflight computers.

The project sits inside NASA’s Space Technology Mission Directorate through the agency’s Game Changing Development program. JPL leads the technical work with Microchip, and NASA Langley Research Center hosts the program management element. The structure reflects a public-private model in which NASA sets demanding mission requirements and industry develops a product family with broader market use.

Microchip formally introduced the PIC64-HPSC family in July 2024. The company described the family as 64-bit high-performance spaceflight computing microprocessors for NASA, defense, and commercial aerospace users. That commercial path matters because NASA can reduce the risk of a one-off government-only chip, and Microchip can pursue non-NASA customers with similar needs.

The defense and security market is a logical early user category because many national security space systems require radiation tolerance, secure processing, autonomous operation, and high-speed data handling. Commercial satellite operators may also value the radiation-tolerant version for low Earth orbit systems that need more onboard networking, payload processing, or edge computing without paying for deep-space-grade protection.

This model does not guarantee rapid adoption. Spacecraft prime contractors, satellite manufacturers, mission software teams, insurers, and government customers will need qualification data, board-level products, software maturity, supply assurance, and pricing clarity. A processor family becomes influential only when designers can integrate it into flight computers with predictable cost and schedule.

HPSC Could Change Mission Operations and Science Return

A faster flight processor can change what mission teams ask a spacecraft to do. On a Mars rover, higher onboard computing capacity can support more advanced navigation, terrain classification, science target selection, and data triage. On an orbiter, it can help sort instrument data and manage high-speed sensor flows. On a lunar lander, it can support hazard detection and descent processing during time-sensitive operations.

The Artemis program creates another possible use case. Future lunar surface systems may include landers, rovers, habitats, power systems, communications nodes, and scientific payloads. Each element will need computing that balances reliability, autonomy, crew safety, power constraints, and maintainability. HPSC could support some of those functions once it completes qualification and mission designers adopt it.

Earth science spacecraft can also benefit. Sensors looking at weather, oceans, land surfaces, wildfires, atmospheric gases, or ice can generate data faster than downlinks can deliver every byte. Onboard processing can help identify events, compress imagery, detect changes, or select data segments for rapid transmission. This is especially relevant for constellations and small satellites that operate with limited communications time.

Commercial satellite operators may use similar capabilities for payload processing. Instead of downlinking every raw data stream to ground stations, a satellite can process more data in orbit, send only selected results, and support lower-latency services. That approach can matter for Earth observation analytics, communications routing, space domain awareness, and hosted payloads.

The effect on science is not just faster computing. Better onboard processing can influence mission architecture. Designers may add more capable sensors, plan more autonomous observation campaigns, or use networked processors to handle payloads that would have been too demanding for older flight computers. HPSC may also reduce reliance on specialized one-off computing boards if standard processor products become easier to buy and qualify.

Space Computing Connects to Standards, Software, and Supply Chain

Flight processors succeed only when the surrounding hardware and software mature with them. Microchip’s product page lists development boards, board support packages, operating system support, compilers, libraries, firmware, and interfaces. Those supporting pieces matter because mission engineers need more than a bare chip; they need a working computing platform that can pass design reviews and survive mission assurance scrutiny.

Software support is especially important for HPSC because modern multi-core processors require careful software architecture. Engineers must decide which tasks run on which cores, how data moves between processors and instruments, how faults are detected, and how safety limits override routine processing. Operating systems, hypervisors, and real-time software tools shape whether missions can use the hardware effectively.

Networking standards also matter. Spacecraft increasingly connect instruments, sensors, payload processors, radios, power units, and avionics using higher-speed data paths. Microchip lists SpaceWire, Ethernet TSN, PCIe, and CXL support in the PIC64-HPSC family. These interfaces can help future spacecraft move more data internally, although mission adoption will depend on board design, radiation testing, and system-level qualification.

The supply-chain angle deserves attention. Space-grade electronics have different economics from consumer chips. Volumes are smaller, qualification is expensive, lead times can be long, and customers often need continuity for missions that span many years. A commercial product family with both radiation-hardened and radiation-tolerant versions could help broaden demand, but high-reliability aerospace procurement will still require documentation, testing, and long-term support.

Security is another factor. Microchip lists secure boot, crypto acceleration, anti-tamper features, and post-quantum cryptography among product capabilities. Spacecraft increasingly function as nodes in larger data networks, and onboard processors may handle sensitive command, navigation, science, or defense and security data. Better onboard computing expands capability, but it also increases the need for disciplined software assurance and cyber protection.

The following table shows how HPSC fits into the broader space economy rather than only NASA exploration missions.

Certification and Adoption Will Decide the Processor’s Real Impact

As of May 2026, HPSC has reached a strong technical milestone, but the larger test is adoption. NASA expects the project to conclude once testing demonstrates space qualification. After that, individual missions still need to select the processor, design boards around it, write and validate software, qualify the full flight computer, and accept the risk profile.

Certification is not a single switch. A chip may pass radiation tests, yet mission teams still need board-level qualification and system-level analysis. A processor may demonstrate high performance, yet flight software must be written to use it safely. A product may support many interfaces, yet spacecraft contractors must decide which interfaces to include in their avionics designs.

Schedule timing also matters. Missions already deep into design may continue with existing flight computers because late hardware changes can threaten launch dates. New missions, technology demonstrations, commercial satellite platforms, and next-generation lunar systems may have more room to adopt HPSC. Early access partners in defense and commercial aerospace could help mature the product family before broader use.

Cost will also influence adoption. Radiation-hardened electronics are expensive relative to terrestrial components, and buyers will compare HPSC against existing processors, field-programmable gate arrays, graphics processors, and custom payload-processing boards. The processor’s value case will depend on total system cost, software reuse, power savings, data-handling gains, and reduced operational burden.

The most realistic near-term expectation is gradual use rather than an immediate fleet-wide replacement. HPSC may first appear in technology demonstrations, selected payload processors, advanced rovers, landers, or spacecraft that need high onboard processing. Wider use would follow once developers gain flight experience and mission assurance teams build confidence in its behavior.

Summary

NASA’s HPSC testing milestone marks an important step in the long effort to bring stronger computing into spacecraft without sacrificing reliability. The May 2026 JPL test campaign places the processor into radiation, thermal, shock, performance, and functional evaluation, moving it from design achievement toward the harder question of flight readiness.

The processor’s value comes from the combination of radiation tolerance, multi-core performance, modern interfaces, power management, security features, and software support. Those attributes point toward a future in which spacecraft can process more data near the source, make more time-sensitive decisions on board, and support missions that operate farther from direct human control.

HPSC also shows how NASA technology development can connect exploration needs with commercial aerospace demand. Microchip’s PIC64-HPSC family gives NASA a path toward higher-performance flight computing and gives the market a processor line that could serve government, commercial, and defense users. Qualification results, board-level products, software maturity, and early flight experience will decide how widely the processor influences spacecraft design.

Appendix: Useful Books Available on Amazon

• Spacecraft Systems Engineering
• Space Mission Engineering
• Spacecraft Attitude Determination and Control
• Fundamentals of Spacecraft Attitude Determination and Control
• How Spacecraft Fly

Appendix: Top Questions Answered in This Article

What Is NASA’s HPSC Processor?

NASA’s High Performance Spaceflight Computing processor is a next-generation spacecraft processor developed to increase onboard computing power for future missions. It is designed to tolerate radiation and other space conditions, support autonomy, process sensor and science data, and reduce dependence on slower ground-based decision cycles during time-sensitive mission events.

Why Does Spacecraft Computing Need Special Processors?

Spacecraft computers face radiation, temperature extremes, launch stress, limited power, and long operating lives without physical repair. These conditions make ordinary terrestrial chips unsuitable for many missions. Space processors must emphasize fault tolerance, radiation resistance, predictable behavior, and mission assurance as strongly as raw speed.

What Did NASA Announce in May 2026?

NASA announced that its HPSC processor was undergoing testing at JPL. The test campaign includes radiation, thermal, shock, performance, and functional evaluations. NASA reported early indications that the processor was working as designed and showing very high performance compared with existing radiation-hardened space chips.

Who Is Building the HPSC Processor?

Microchip Technology is building the HPSC processor family in partnership with NASA and JPL. NASA selected Microchip in 2022 to develop the processor, and Microchip introduced the PIC64-HPSC family in 2024. NASA sets mission-driven requirements, and Microchip provides a commercial product path for government and aerospace customers.

What Missions Could Use HPSC?

NASA identifies Earth orbiters, planetary rovers, crewed habitats, deep-space missions, lunar missions, and Mars systems as possible users after qualification. Commercial satellite platforms and defense aerospace systems may also use variants of the processor where radiation tolerance, secure processing, networking, and onboard data handling are valuable.

How Does HPSC Help Autonomous Spacecraft?

HPSC gives spacecraft more onboard computing capacity to process images, classify data, run navigation logic, and respond to changing conditions. That can help landers assess hazards, rovers select safer paths, orbiters prioritize data, and deep-space probes operate during periods when communication delays prevent real-time ground control.

What Is a System-On-a-Chip?

A system-on-a-chip combines many computer functions on one integrated circuit. In HPSC’s case, the chip includes processing cores, computational support blocks, networking units, memory interfaces, and input/output functions. This helps reduce size, mass, and power use compared with larger computing assemblies built from many separate chips.

What Is the Difference Between Radiation-Hardened and Radiation-Tolerant Versions?

The radiation-hardened PIC64-HPSC1000 is intended for harsher mission profiles such as medium Earth orbit, geostationary Earth orbit, and deep space. The radiation-tolerant PIC64-HPSC1100 is aimed at low Earth orbit and commercial satellite missions. The two versions give designers choices based on mission environment and cost.

Will HPSC Immediately Replace Existing Spacecraft Computers?

HPSC is unlikely to replace existing spacecraft computers all at once. Missions already far into design may keep their selected avionics. Adoption will likely begin with missions that need high onboard processing, early demonstration opportunities, and platforms where the new processor’s performance justifies qualification effort and integration cost.

Why Does HPSC Matter to the Space Economy?

HPSC matters because computing capacity shapes what spacecraft can do in orbit, on planetary surfaces, and during deep-space operations. Stronger onboard processing supports higher-value data services, autonomous operations, commercial satellite payload processing, defense and security missions, and future exploration systems that need local decision support.

Appendix: Glossary of Key Terms

National Aeronautics and Space Administration

The National Aeronautics and Space Administration is the United States civilian space agency. In this article, NASA is the sponsoring agency for the High Performance Spaceflight Computing project and the source of the May 2026 testing announcement.

High Performance Spaceflight Computing

High Performance Spaceflight Computing is NASA’s project to develop a next-generation flight computing system for future missions. It targets greater computational performance, power management, fault tolerance, connectivity, and support for autonomy through 2040 and beyond.

Jet Propulsion Laboratory

Jet Propulsion Laboratory is a NASA center managed by Caltech in Southern California. JPL leads many robotic exploration missions and is conducting the HPSC processor testing described in NASA’s May 2026 announcement.

Radiation Hardening

Radiation hardening refers to design and manufacturing techniques that help electronics survive the radiation environment of space. It reduces the risk of damage, data corruption, and operational faults caused by energetic particles.

System-On-a-Chip

A system-on-a-chip is an integrated circuit that combines many computer components into one chip. HPSC uses this approach to package processing, networking, memory interfaces, and input/output functions into a compact spacecraft processor.

RISC-V

RISC-V is an open instruction set architecture used to design processors. Microchip’s PIC64-HPSC family uses 64-bit RISC-V cores, which support modern computing features and specialized processing needed for spaceflight applications.

Artificial Intelligence

Artificial intelligence refers to software techniques that allow computers to perform tasks such as classification, detection, planning, or decision support. In spacecraft, AI can help process sensor data and support autonomous actions within mission-approved limits.

Machine Learning

Machine learning is a form of artificial intelligence in which software improves task performance through patterns learned from data. Spacecraft applications can include image classification, anomaly detection, terrain recognition, and data prioritization.

Time-Sensitive Networking

Time-Sensitive Networking is a family of Ethernet standards that supports more predictable data delivery. In spacecraft systems, TSN can help manage timing-sensitive data flows between processors, sensors, instruments, and other onboard systems.

SpaceWire

SpaceWire is a spacecraft data communication standard used for links between onboard instruments, processors, mass memory, and other electronics. It supports reliable data movement inside spacecraft avionics and payload systems.

Peripheral Component Interconnect Express

Peripheral Component Interconnect Express, usually called PCIe, is a high-speed interface standard used to connect processors with other devices. In spacecraft computing, it can support fast internal links where qualified hardware and mission design permit its use.

Compute Express Link

Compute Express Link is an interface standard designed for high-speed connections among processors, memory, and accelerators. Its inclusion in HPSC-related product descriptions shows the processor family’s alignment with modern high-throughput computing architectures.

Low Earth Orbit

Low Earth orbit is an orbital region relatively close to Earth, commonly used by Earth observation satellites, communications constellations, crewed spacecraft, and technology demonstrations. Microchip describes one HPSC variant as suited to LEO and commercial satellite mission profiles.

Deep Space

Deep space refers to regions beyond Earth orbit where communication delays, radiation exposure, and distance from repair infrastructure make autonomy and reliability especially important. HPSC is designed to support missions that operate far from direct ground intervention.